The approach of employing three-dimensional chip stacking can enable wire shortening and other design strategies. This triggers a process of moving data or instructions from the slower memory levels to faster ones where they may be used only a few times and then must be "retired" or moved back to slower memory if values are altered. Each time the processor cannot find an instruction or data item in one of the lower, fast levels of this cache memory system one obtains a "miss" and the access must be taken from a higher and slower level. As processor speeds increase towards 10 GHz and higher, the size of the larger, slower levels of cache must increase in order to keep providing useful data and instructions to the processor (Amdahl's Law). Here conventional two dimensional or planar packaging limits the number of the interconnections between the processor and the memory and requires off-chip interconnections between dies. At the highest level of the hierarchy for memory the largest and slowest memory blocks are found. In middle level cache memories one encounters long bit and word lines.
As one progresses up this hierarchy one encounters larger, even slower levels of memory. Wire parasitics in memory blocks impact performance all throughout the memory hierarchy, from the lowest level of primary cache through. One of the ways interconnections play a role is in the limitation imposed on access of various levels of memory. It is now widely acknowledged that interconnections are having an increasingly adverse impact on the speed of computers through wiring delay. These features make the HMRL as perhaps one fo the well designed and developed project that has been executed with perfection. The technical analysis covers the details of metro rail route alignment, horizontal, vertical and cross-sectional details of structure, design of the project structures, construction methods and processes, operational arrangements etc. This paper discusses the salient technical features of the HMRP towards addressing traffic and transportation of the Hyderabad city. The HMRL project suffered from several challenges and yet it is on the verge of completion in terms of technical execution. Recognising this, the Hyderabad Metro Rail Project (HMRP) was planned to be developed as a Public-Private Partnership (PPP) model in India. As the existing transportation modes – buses and trains – are already saturated, there is a need for developing Mass Rapid Transit Systems (MRTS). Hyderabad city is a large metropolitan city in India which has a high level of population and the traffic and transportation problems are rising over the past several years.